Conventional systems use coefficient multipliers in digital filters, such as with a Finite Impulse Response (FIR) filters, as well as within other applications. The multiplier may contain set of coefficients. The coefficients are multiplied with operands that are supplied to the multiplier. Each operand may be multiplied by a coefficient. The product is presented on the output for use within the next level (i.e., a summation of the products).
Conventional multipliers are generally implemented with combinations of shift and add operations. Some such implementations have a high gate count, which can result in an inefficient use of chip area.
It would be desirable to implement a multiplier that may be implemented with a minimal number of shift and add operations and/or may be implemented using a minimal amount of chip area.